A pipeline analog to digital converter (ADC) architecture may include stage amplifiers. The number of stage amplifiers may be substantially equal to the number of output bits. The output bits may indicate the instantaneous amplitude level of an analog signal. The stage amplifier may receive an analog signal and according to a clock signal may compare the analog signal to a reference voltage level. The comparison result of the stage amplifier may be outputted in the form of an output voltage level that may be translated to values of logic bits. Furthermore, the stage amplifier may output one or two bits to provide a digital value to the sample of the analog signal. However, the output voltage of the stage amplifier may need to be adapted to a required output voltage level within a given range, e.g., a given error window. One solution of enabling the stage amplifier to adapt to the required output voltage level range within the given error window nay be to provide a large current to the stage amplifier. The large current may increase a slew rate and a bandwidth of the stage amplifier. A large charge current may increase a power consumption of the stage amplifier.
Thus, there is a need to provide a pipeline ADC which mitigates the above-described disadvantage.